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Computer Architecture

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		^Votes:0 << 2007-8 >> Home \| Index \| People \| Research \| Publications Department of Computer Science Welcome to the world of the Data Diffusion Machine . The Data Diffusion Machine (DDM) is a virtual shared memory architecture where data is free to migrate through the machine. We have the following to offer: A DDM primer . A list of publications about the DDM. Abstracts and Postscript versions of recent articles. A demo of our DDM performance monitor . A list of pointers to related work . A list of people involved with the DDM at Bristol. Primer on the Data Diffusion Machine Shared memory machines are convenient for programming but do not scale beyond tens of processors. The Data Diffusion Machine (DDM) overcomes this problem by providing a virtual memory abstraction on top of a distrib Read More Go to Site


		Von Neumann Architecture » PC Mechanic ^Votes:0 CLOSE You've Found Us! Now Stay Connected... Sign Up for PCMech.com's FREE weekly newsletter: Privacy Policy \| More Information PCMech.com, a blog covering technology, computers and the Internet. Home \| About \| Newsletter \| Forums \| RSS \| Shop.PCMech \| Membership \| Login Home News Wire Forums Comics Store How Do I Podcast Videos Ask Us Dave's Faves Helping Normal People Get Their Geek On Latest From The Wire Links to Reviews from Nov 19-21 Apples Continues to be Cocky Thanksgiving Wikipedia Stuff to Educate Your Brain Oprah Admits YouTube Comments Are a Problem 3 Quick Tips for Faster IMAP Gmail in Mozilla Thunderbird Subscribe to PC Mechanic Subscribe via RSS What is RSS? Or, via email. Follow PCMech on Twitter PCMech Sponsors Advertise on PCMech Sponsor Who Visits Von Neumann Architectur Read More Go to Site

		Central Processing Unit ^Votes:0 Central Processing Unit Gerald Neufeld UBC Computer Science Central Processing Unit Arithmetic Logic Unit Basic CPU Components Three Schools of CPU Design Stack Based Design Pros/Cons of stack machines: General Purpose Register Design Example of CPU Internal design choices 2-bus design 3 bus design More on 3 buses Memory Interface Harvard School Examples of CPUs Intel 80x86 History Intel history Moore?s Law Instruction Formats Addressing Modes Addressing Modes Addressing Modes Program Control Conditional Branch Subroutine Call and Return Interrupts Interrupt Vector Types of Interrupts CISC / RISC Intel 432 (worst case example) RISC Read More Go to Site

		Index for Parallel and Distributed Computing Notes ^Votes:0 Distributed Computing : An Overview Introduction to Load Balancing and Scheduling Static Scheduling Task Granularity and Partitioning Scheduling Tools Load Balancing Mechanisms for Process Migration Load Indices Other Links of Interest Click to go back to index This page hosted by Get your own Free Home Page Read More Go to Site

		Shared-Memory Architectures ^Votes:0 Next: Optimized Send and Up: Multiprocessor Systems Previous: Message-Passing Architectures Shared-Memory Architectures The shared-memory architecture provides a very efficient medium for processes to exchange data. In our implementation, each task owns a shared buffer created with the shmget() system call. The task id is used as the ``key" to the shared segment. If the key is being used by another user, PVM will assign a different id to the task. A task communicates with other tasks by mapping their message buffers into its own memory space. To enroll in PVM, the task first writes its Unix process id into pvmd's incoming box. It then looks for the assigned task id in pvmd's pid->TID table. The message buffer is divided into pages, each of which holds one fragment (Figure ). PVM's pag Read More Go to Site

		Terms and Definitions ^Votes:0 Computer Engineering (Processors) Terms and Definitions Version: December 2, 1997 This is the proposed list of terms with definitions. If you feel some terms are missing or you can add or correct definitions, please send me email (jza@ece.engr.ucf.edu). Initials denote the author who proposed/defined this term. Definitions marked CRC have been taken from other CRC publications. Please note that memory and I/O terms are out of scope of our group (there is a separate group defining those), so in principle we should not waste our time for providing these definitions. A abnormal event (interrupt type) Any external or program-generated event that makes further normal program execution impossible or undesirable, resulting in a system interrupt. Examples: system detection of power failure, attemp Read More Go to Site

		ALI Recent Papers ^Votes:0 Architecture & Language Implementation Recent Publications This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's or organization's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. This page includes links to compressed postscript files of papers written by members of the ALI group. Compiler Architectures The Common Language Encoding Form (CLEF) Design Document , Glen E. Weaver , Brendon D. Cahoon , J. Eliot B. Moss , K. S. McKinley , Eric J. Wright , James H. Burrill , University of Mass Read More Go to Site

		Avalanche Project Publications ^Votes:0 University of Utah Department of Computer Science Avalanche Scalable Parallel Processor Project Publications ASCOMA: An Adaptive Hybrid Shared Memory Architecture (ICPP98 -- Aug 1998) Abstract Scalable shared memory multiprocessors traditionally use either a cache coherent non-uniform memory access (CC-NUMA) or simple cache-only memory architecture (S-COMA) memory architecture. Recently, hybrid architectures that combine aspects of both CC-NUMA and S-COMA have emerged. In this paper, we present two improvements over other hybrid architectures. The first improvement is a page allocation algorithm that prefers S-COMA pages at low memory pressures. Once the local free page pool is drained, additional pages are mapped in CC-NUMA mode until they suffer sufficient remote misses to warrant upgrad Read More Go to Site

		Content Moved ^Votes:0 Content Moved This section has moved. Click here if your browser doesn't support Refresh tags. Read More Go to Site

		Digital Logic ^Votes:0 Home www.play-hookey.com Thu, 11-01-2007 Digital \| Logic Families \| Digital Experiments \| Analog \| Analog Experiments \| DC Theory \| AC Theory \| Optics \| Computers \| Semiconductors \| Test HTML Direct Links to Other Digital Pages: Combinational Logic: [ Basic Gates ] [ Derived Gates ] [ The XOR Function ] [ Binary Addition ] [ Negative Numbers and Binary Subtraction ] [ Multiplexer ] [ Decoder/Demultiplexer ] [ Boolean Algebra ] Sequential Logic: [ RS NAND Latch ] [ RS NOR Latch ] [ Clocked RS Latch ] [ RS Flip-Flop ] [ JK Flip-Flop ] [ D Latch ] [ D Flip-Flop ] [ Flip-Flop Symbols ] [ Converting Flip-Flop Inputs ] Alternate Flip-Flop Circuits: [ D Flip-Flop Using NOR Latches ] [ CMOS Flip-Flop Construction ] Counters: [ Basic 4-Bit Counter ] [ Synchronous Binary Counter ] [ Synchronous Deci Read More Go to Site

		George B. Adams III home page ^Votes:0 Dr. George B. Adams III Associate Director for Programs Network for Computational Nanotechnology Purdue University BRK 1287B (office) 1205 West State Street West Lafayette, IN 47907-2057 g b a @purdue.edu +1 765 494 2698 (phone) +1 765 496 8383 (fax) Research Interests Nanotechnology, computer architecture, and algorithms. Teaching Awards National Technological University Outstanding Instructor award, 1995 and 2003. Other Vice President of the Board of Directors of the Lafayette Symphony Orchestra, Inc. Copyright&copy by George B. Adams III This page was last modified October 15, 2007 . Read More Go to Site

		PCGuide - Ref - Processor Architecture and Operation ^Votes:0 Welcome to The PC Guide! It seems that either your browser does not support frames, or you have them disabled. The PC Guide makes extensive use of frames to facilitate easier navigation through the site. The PC Guide site uses a hierarchical structure of pages. The general rule of thumb is that the information on the site is displayed in the "Contents" frame, called "C", while the links deeper into the structure are in the "Index" frame, called "I". You can find information on the site without using frames in three different ways: Some text browsers, like Lynx, don't support frames but allow browsing of framed sites by providing links to each frame from this page. If you see links to "I" and "C" above this text, you can use these Read More Go to Site

		PiSMA Computer Home Page ^Votes:0 PiSMA Architecture Research Group Dept. of Computer Engineering & Informatics Univercity of Patras, Greece The P i SMA Home Page P i SMA ( P arallel V i rtually S hared- M emory A rchitecture ) is a new parallel multiprocessor architecture combining the best of shared and distributed memory designs. The result is a very scalable design (up to 100's of processors) without bus bottleneck problems due to its distributed memory scheme, being at the same time easily programmable , as a partial shared memory design. PiSMA related topics available: An illustrated description of the PiSMA Architecture. Papers and Publications on PiSMA architecture. This site was awarded by StudyWeb as one of the best educational resources on the Web. ( review ) Read More Go to Site

		Redirect.. ^Votes:0 Redirect.. Read More Go to Site

		Smart Computing Article Search Results: Articles in the category ^Votes:0 Subscribe Today \| Contact Us \| Register Now Home \| Tech Support \| Q&A Board \| Article Search \| Subscribe & Shop Smart Computing Articles You Searched For: Articles in the category within the publication(s) ALL PUBLICATIONS and published on or after 11/2005 Number of Matches: 0 Change Your Search Sorry, your search resulted in no matches. Please try selecting a different item or typing in a different phrase. Sorry, there are no sub-categories under this category. Try changing the content of a search field. You might also try leaving one or more of the search fields blank. OR Select an article type: All Article Types General Information Articles Troubleshooting Articles Tutorial Articles Hardware Review Articles Software Review Articles Type in a phrase or key words below, Select Search type Read More Go to Site

		stac.org ^Votes:0 Stac.org What you need, when you need it /* lang_nav --------------------------------------------------/ ul#lang_nav { position: absolute; overflow: visible; top: 19px; right: 0px; z-index: 9999; width: 120px; height: auto; margin: 0px; padding: 0px; border-top: 2px solid #777777; border-left: 2px solid #777777; border-bottom: 1px solid #848484; border-right: 1px solid #848484; text-align: left; background: #ffffdb; opacity: 0.75; filter:alpha(opacity=75); / IE's opacity */ } ul#lang_nav li { position: relative; z-index: 9990; list-style: none; display: block; overflow: visible; width: 100%; margin: 0px; padding: 0px; color: #0707cd; } ul#lang_nav li a { position: relative; z-index: 9991; display: block; width: auto; margin: 0px; padding: 1px 6px; color: #0000cc; font-weight: normal; tex Read More Go to Site

		The TUNES Project to Redefine Computing ^Votes:0 The TUNES Project to Redefine Computing TUNES is a worldwide, loose-knit group of computer enthusiasts working to lay the social and technical foundations for a new vision of computing, based on the principle of Computing Freedom , where everyone can program computers, limited only by their wit and determination. If this interests you, take a look at these writings , starting with the Root subproject. (This is mostly older material, and too long-winded, but it's the best overall description of TUNES available.) There's also a new, oversimplified Overview and Technical Summary which may also enlighten you -- just be aware that it's not fully accurate. Contact Us Mailing List: tunes@tunes.org - (Un)Subscribe IRC: irc.freenode.net #tunes Member List Website problems? Contact Tom Novelli (tcn) Read More Go to Site

		Welcome to Multimedia Teaching of Introductory Digital Systems tutorial ^Votes:0 Welcome to Multimedia Teaching of Introductory Digital Systems tutorial. This is the third part of the series of online tutorial developed by the Department of Electrical Engineering on the teaching of Introductory Digital Systems. This tutorial extends from the previous tutorial on basic flip-flops into sequential circuits. In this tutorial, you will learn the basic concept of sequential circuits, how to analyse a simple sequential circuit using step by step procedures. You will also learn how to design a simple sequential circuit using the various types of flip-flops. In order to understand the concepts of sequential circuits, students are assumed to have learnt the basic concepts of flip-flops which can be found from the previous tutorial. The University of Sydney Department of Electric Read More Go to Site

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